
%SKX_UCFilterAliases = 
(
   "CHAFilter0"     => "C{i}_MSR_PMON_BOX_FILTER0",
   "CHAFilter1"     => "C{i}_MSR_PMON_BOX_FILTER1",
   "PCUFilter"      => "PCU_MSR_PMON_BOX_FILTER",
   "M2MOpcMask"     => "M2M{i}_PCI_PMON_OPCMASK", 
   "M2MAddrMask0"   => "M2M{i}_PCI_PMON_ADDRMASK0", 
   "M2MAddrMask1"   => "M2M{i}_PCI_PMON_ADDRMASK1", 
   "M2MAddrMatch0"  => "M2M{i}_PCI_PMON_ADDRMATCH0", 
   "M2MAddrMatch0"  => "M2M{i}_PCI_PMON_ADDRMATCH1", 
   "UBoxFilter"     => "U_MSR_PMON_BOX_FILTER",
);



%SKX_UCDerivedList =
(
   "CHA Box Events" =>
   {
      "AVG_CRD_MISS_LATENCY" =>
      {
         Category => "TOR Events",
         Filter   => "(CHAFilter1[28:19] | CHAFilter1[18:9])",
         Desc     => "Average Code Read Latency",
         Defn     => "Average Latency of Code Reads from an iA Core that miss the LLC",
         Equation => "(TOR_OCCUPANCY.IA_MISS / TOR_INSERTS.IA_MISS) with:Cn_MSR_PMON_BOX_FILTER1.{opc1,opc0,not_nm,nm,all_opc,loc,rem}={0x259,0x201,1,1,0,1,1}",
      },
      "AVG_DEMAND_RD_HIT_LATENCY" =>
      {
         Category => "TOR Events",
         Filter   => "(CHAFilter1[28:19] | CHAFilter1[18:9])",
         Desc     => "Average Data Read Hit Latency",
         Defn     => "Average Latency of Data Reads that hit the LLC",
         Equation => "(TOR_OCCUPANCY.ALL_HIT / (TOR_INSERTS.ALL_HIT with:Cn_MSR_PMON_BOX_FILTER1.{opc0,not_nm,nm,all_opc,loc,rem}={0x202,1,1,0,1,1}",
      },
      "AVG_DEMAND_RD_MISS_LOCAL_LATENCY" =>
      {
         Category => "TOR Events",
         Filter   => "(CHAFilter1[28:19] | CHAFilter1[18:9]), CHAFilter1[1:0]",
         Desc     => "Average Data Read Local Miss Latency",
         Defn     => "Average Latency of Data Reads from an IA Core that miss the LLC and were satsified by Local Memory",
         Equation => "(TOR_OCCUPANCY.IA_MISS / TOR_INSERTS.IA_MISS) with:Cn_MSR_PMON_BOX_FILTER1.{opc0,not_nm,nm,all_opc,loc,rem}={0x202,1,1,0,1,0}",
      },
      "AVG_DRD_MISS_LATENCY" =>
      {
         Category => "TOR Events",
         Filter   => "(CHAFilter1[28:19] | CHAFilter1[18:9])",
         Desc     => "Average Data Read Miss Latency",
         Defn     => "Average Latency of Data Reads or Data Read Prefetches from an IA Core that miss the LLC",
         Equation => "(TOR_OCCUPANCY.IA_MISS / TOR_INSERTS.IA_MISS) with:Cn_MSR_PMON_BOX_FILTER1.{opc1, opc0,not_nm,nm,all_opc,loc,rem}={0x25A,0x202,1,1,0,1,1}",
      },
      "AVG_IA_CRD_LLC_HIT_LATENCY" =>
      {
         Category => "TOR Events",
         Filter   => "(CHAFilter1[28:19] | CHAFilter1[18:9])",
         Desc     => "Average Code Read Latency",
         Defn     => "Average Latency of Code Reads from an iA Core that miss the LLC",
         Equation => "(TOR_OCCUPANCY.IA_HIT / TOR_INSERTS.IA_HIT) with:Cn_MSR_PMON_BOX_FILTER1.{opc0,not_nm,nm,all_opc,loc,rem}={0x201,1,1,0,1,1}",
      },
      "AVG_INGRESS_DEPTH" =>
      {
         Category => "INGRESS Events",
         Filter   => "",
         Desc     => "Average Ingress (from CMS) Depth",
         Defn     => "Average Depth of the Ingress Queue through the sample interval",
         Equation => "RxC_OCCUPANCY.IRQ  / SAMPLE_INTERVAL",
      },
      "AVG_INGRESS_LATENCY" =>
      {
         Category => "INGRESS Events",
         Filter   => "",
         Desc     => "Average Ingress (from CMS) Latency",
         Defn     => "Average Latency of Requests through the Ingress Queue in Uncore Clocks",
         Equation => "RxC_OCCUPANCY.IRQ / RxC_INSERTS.IRQ",
      },
      "AVG_INGRESS_LATENCY_WHEN_NE" =>
      {
         Category => "INGRESS Events",
         Filter   => "",
         Desc     => "Average Latency in Non-Empty Ingress (from CMS)",
         Defn     => "Average Latency of Requests through the Ingress Queue in Uncore Clocks when Ingress Queue has at least one entry",
         Equation => "RxC_OCCUPANCY.IRQ / COUNTER0_OCCUPANCY{edge_det,thresh=0x1}",
      },
      "AVG_RFO_MISS_LATENCY" =>
      {
         Category => "TOR Events",
         Filter   => "(CHAFilter1[28:19] | CHAFilter1[18:9])",
         Desc     => "Average RFO Latency",
         Defn     => "Average Latency of RFOs from an iA Core that miss the LLC",
         Equation => "(TOR_OCCUPANCY.IA_MISS / TOR_INSERTS.IA_MISS) with:Cn_MSR_PMON_BOX_FILTER1.{opc0,not_nm,nm,all_opc,loc,rem}={0x200,1,1,0,1,1}",
      },
      "AVG_TOR_DRDS_MISS_WHEN_NE" =>
      {
         Category => "TOR Events",
         Filter   => "(CHAFilter1[28:19] | CHAFilter1[18:9])",
         Desc     => "Average Data Read Misses in Non-Empty TOR",
         Defn     => "Average Number of Data Read Entries that Miss the LLC when the TOR is not empty.",
         Equation => "(TOR_OCCUPANCY.ALL_MISS / COUNTER0_OCCUPANCY{edge_det,thresh=0x1})) with:Cn_MSR_PMON_BOX_FILTER1.{opc0,not_nm,nm,all_opc,loc,rem}={0x202,1,1,0,1,1}",
      },
      "AVG_TOR_DRDS_WHEN_NE" =>
      {
         Category => "TOR Events",
         Filter   => "(CHAFilter1[28:19] | CHAFilter1[18:9])",
         Desc     => "Average Data Reads in Non-Empty TOR",
         Defn     => "Average Number of Data Read Entries when the TOR is not empty.",
         Equation => "(TOR_OCCUPANCY.ALL / COUNTER0_OCCUPANCY{edge_det,thresh=0x1}) with:Cn_MSR_PMON_BOX_FILTER1.{opc0,not_nm,nm,all_opc,loc,rem}={0x202,1,1,0,1,1}",
      },
      "CYC_INGRESS_BLOCKED" =>
      {
         Category => "INGRESS Events",
         Filter   => "",
         Desc     => "Cycles Ingress (from CMS) Blocked",
         Defn     => "Cycles the Ingress Request Queue arbiter was Blocked",
         Equation => "RxC_EXT_STARVED.IRQ  / SAMPLE_INTERVAL",
      },
      "FAST_STR_LLC_HIT" =>
      {
         Category => "TOR Events",
         Filter   => "(CHAFilter1[28:19] | CHAFilter1[18:9])",
         Desc     => "Fast String operations",
         Defn     => "Number of ItoM (fast string) operations that reference the LLC",
         Equation => "TOR_INSERTS.IA_HIT with:Cn_MSR_PMON_BOX_FILTER1.{opc0,not_nm,nm,all_opc,loc,rem}={0x248,1,1,0,1,1}",
      },
      "FAST_STR_LLC_MISS" =>
      {
         Category => "TOR Events",
         Filter   => "(CHAFilter1[28:19] | CHAFilter1[18:9])",
         Desc     => "Fast String misses",
         Defn     => "Number of ItoM (fast string) operations that miss the LLC",
         Equation => "TOR_INSERTS.IA_MISS with:Cn_MSR_PMON_BOX_FILTER1.{opc0,not_nm,nm,all_opc,loc,rem}={0x248,1,1,0,1,1}",
      },
      "INGRESS_REJ_V_INS" =>
      {
         Category => "INGRESS Events",
         Filter   => "",
         Desc     => "Ingress (from CMS) Rejects vs. Inserts",
         Defn     => "Ratio of Ingress Request Entries that were rejected vs. inserted",
         Equation => "RxC_INSERTS.IRQ_REJECTED  / RxC_INSERTS.IRQ",
      },
      "LLC_CRD_MISS_TO_LOC_MEM" =>
      {
         Category => "TOR Events",
         Filter   => "(CHAFilter1[28:19] | CHAFilter1[18:9]), CHAFilter1[1:0]",
         Desc     => "LLC Code Read Misses to Local Memory",
         Defn     => "LLC Code Read and Code Prefetch misses satisfied by local memory.",
         Equation => "TOR_INSERTS.IA_MISS  with:Cn_MSR_PMON_BOX_FILTER1.{opc1,opc0,not_nm,nm,all_opc,loc,rem}={0x259,0x201,1,1,0,1,0})",
      },
      "LLC_CRD_MISS_TO_REM_MEM" =>
      {
         Category => "TOR Events",
         Filter   => "(CHAFilter1[28:19] | CHAFilter1[18:9]), CHAFilter1[1:0]",
         Desc     => "LLC Code Read Misses to Remote Memory",
         Defn     => "LLC Code Read and Code Read Prefetch misses satisfied by a remote cache or remote memory.",
         Equation => "TOR_INSERTS.IA_MISS  with:Cn_MSR_PMON_BOX_FILTER1.{opc1,opc0,not_nm,nm,all_opc,loc,rem}={0x259,0x201,1,1,0,0,1})",
      },
      "LLC_DRD_MISS_PCT" =>
      {
         Category => "CACHE Events",
         Filter   => "CHAFilter0[26:17]",
         Desc     => "LLC DRd Miss Percentage",
         Defn     => "",
         Equation => "LLC_LOOKUP.DATA_READ (Cn_MSR_PMON_BOX_FILTER0.state=0x1) / LLC_LOOKUP.DATA_READ (Cn_MSR_PMON_BOX_FILTER0.state=0xF1)",
      },
      "LLC_DRD_MISS_TO_LOC_MEM" =>
      {
         Category => "TOR Events",
         Filter   => "(CHAFilter1[28:19] | CHAFilter1[18:9]), CHAFilter1[1:0]",
         Desc     => "LLC Data Read Misses to Local Memory",
         Defn     => "LLC Data Read and Data Prefetch misses satisfied by local memory.",
         Equation => "TOR_INSERTS.IA_MISS  with:Cn_MSR_PMON_BOX_FILTER1.{opc1,opc0,not_nm,nm,all_opc,loc,rem}={0x25A,0x202,1,1,0,1,0})",
      },
      "LLC_DRD_MISS_TO_REM_MEM" =>
      {
         Category => "TOR Events",
         Filter   => "(CHAFilter1[28:19] | CHAFilter1[18:9]), CHAFilter1[1:0]",
         Desc     => "LLC Data Read Misses to Remote Memory",
         Defn     => "LLC Data Read and Data Prefetch misses satisfied by a remote cache or remote memory.",
         Equation => "TOR_INSERTS.IA_MISS  with:Cn_MSR_PMON_BOX_FILTER1.{opc1,opc0,not_nm,nm,all_opc,loc,rem}={0x25A,0x202,1,1,0,0,1})",
      },
      "LLC_DRD_PREFETCH_HITS" =>
      {
         Category => "TOR Events",
         Filter   => "(CHAFilter1[28:19] | CHAFilter1[18:9]), CHAFilter1[1:0]",
         Desc     => "DRd Prefetches that Hit the LLC",
         Defn     => "",
         Equation => "TOR_INSERTS.IA_HIT  with:Cn_MSR_PMON_BOX_FILTER1.{opc0,not_nm,nm,all_opc,loc,rem}={0x25A,1,1,0,1,1})",
      },
      "LLC_DRD_PREFETCH_MISSES" =>
      {
         Category => "TOR Events",
         Filter   => "(CHAFilter1[28:19] | CHAFilter1[18:9]), CHAFilter1[1:0]",
         Desc     => "DRd Prefetches that Missed the LLC",
         Defn     => "",
         Equation => "TOR_INSERTS.IA_MISS  with:Cn_MSR_PMON_BOX_FILTER1.{opc0,not_nm,nm,all_opc,loc,rem}={0x25A,1,1,0,1,1})",
      },
      "LLC_IA_CRD_HITS" =>
      {
         Category => "TOR Events",
         Filter   => "(CHAFilter1[28:19] | CHAFilter1[18:9]), CHAFilter1[1:0]",
         Desc     => "LLC Code Read Misses to Local Memory",
         Defn     => "LLC Code Read and Code Prefetch misses satisfied by local memory.",
         Equation => "TOR_INSERTS.IA_HIT  with:Cn_MSR_PMON_BOX_FILTER1.{opc0,not_nm,nm,all_opc,loc,rem}={0x201,1,1,0,1,0})",
      },
      "LLC_MPI" =>
      {
         Category => "CACHE Events",
         Filter   => "CHAFilter0[26:17]",
         Desc     => "LLC MPI",
         Defn     => "LLC Misses Per Instruction (code, read, RFO and prefetches)",
         Equation => "LLC_LOOKUP.ANY (Cn_MSR_PMON_BOX_FILTER0.state=0x1) / INST_RETIRED.ALL (on Core)",
      },
      "LLC_PCIE_DATA_BYTES" =>
      {
         Category => "TOR Events",
         Filter   => "CHAFilter0[8:0], (CHAFilter1[28:19] | CHAFilter1[18:9])",
         Desc     => "LLC Miss Data from PCIe",
         Defn     => "LLC write miss (disk/network reads) bandwidth in MB",
         Equation => "TOR_INSERTS.IO with:Cn_MSR_PMON_BOX_FILTER1.{opc0,not_nm,nm,all_opc,loc,rem}={0x248,1,1,0,1,1} * 64",
      },
      "LLC_RFO_MISS_PCT" =>
      {
         Category => "TOR Events",
         Filter   => "(CHAFilter1[28:19] | CHAFilter1[18:9])",
         Desc     => "LLC RFO Miss Ratio",
         Defn     => "LLC RFO Miss Ratio",
         Equation => "(TOR_INSERTS.ALL_MISS / TOR_INSERTS.ALL) with:Cn_MSR_PMON_BOX_FILTER1.{opc0,not_nm,nm,all_opc,loc,rem}={0x200,1,1,0,1,1}",
      },
      "LLC_RFO_MISS_TO_LOC_MEM" =>
      {
         Category => "TOR Events",
         Filter   => "(CHAFilter1[28:19] | CHAFilter1[18:9]), CHAFilter1[1:0]",
         Desc     => "LLC RFO Misses to Local Memory",
         Defn     => "LLC  RFO and RFO Prefetch misses satisfied by local memory.",
         Equation => "TOR_INSERTS.IA_MISS  with:Cn_MSR_PMON_BOX_FILTER1.{opc1,opc0,not_nm,nm,all_opc,loc,rem}={0x258,0x200,1,1,0,1,0})",
      },
      "LLC_RFO_MISS_TO_REM_MEM" =>
      {
         Category => "TOR Events",
         Filter   => "(CHAFilter1[28:19] | CHAFilter1[18:9]), CHAFilter1[1:0]",
         Desc     => "LLC RFO Misses to Remote Memory",
         Defn     => "LLC RFO and RFO Prefetch misses satisfied by a remote cache or remote memory.",
         Equation => "TOR_INSERTS.IA_MISS  with:Cn_MSR_PMON_BOX_FILTER1.{opc1,opc0,not_nm,nm,all_opc,loc,rem}={0x258,0x200,1,1,0,0,1})",
      },
      "LLC_RFO_PREFETCH_HITS" =>
      {
         Category => "TOR Events",
         Filter   => "(CHAFilter1[28:19] | CHAFilter1[18:9]), CHAFilter1[1:0]",
         Desc     => "RFO Prefetches that Hit the LLC",
         Defn     => "",
         Equation => "TOR_INSERTS.IA_HIT  with:Cn_MSR_PMON_BOX_FILTER1.{opc0,not_nm,nm,all_opc,loc,rem}={0x258,1,1,0,1,1})",
      },
      "LLC_RFO_PREFETCH_MISSES" =>
      {
         Category => "TOR Events",
         Filter   => "(CHAFilter1[28:19] | CHAFilter1[18:9]), CHAFilter1[1:0]",
         Desc     => "RFO Prefetches that Missed the LLC",
         Defn     => "",
         Equation => "TOR_INSERTS.IA_MISS  with:Cn_MSR_PMON_BOX_FILTER1.{opc0,not_nm,nm,all_opc,loc,rem}={0x258,1,1,0,1,1})",
      },
      "MMIO_READ_BW" =>
      {
         Category => "TOR Events",
         Filter   => "CHAFilter0[8:0], (CHAFilter1[28:19] | CHAFilter1[18:9])",
         Desc     => "IO Read Bandwidth",
         Defn     => "IO Read Bandwidth in MB - Disk or Network Reads",
         Equation => "(TOR_INSERTS.IA_MISS  with:Cn_MSR_PMON_BOX_FILTER1.{nc,opc0,not_nm,nm,all_opc,loc,rem}={1,0x20E,1,1,0,1,1} * 64 / 1000000",
      },
      "MMIO_WRITE_BW" =>
      {
         Category => "TOR Events",
         Filter   => "(CHAFilter1[28:19] | CHAFilter1[18:9])",
         Desc     => "IO Write Bandwidth",
         Defn     => "IO Write Bandwidth in MB - Disk or Network Writes",
         Equation => "(TOR_INSERTS.IA_MISS  with:Cn_MSR_PMON_BOX_FILTER1.{nc,opc0,not_nm,nm,all_opc,loc,rem}={1,0x20F,1,1,0,1,1} * 64 / 1000000",
      },
      "PCIE_FULL_WRITES" =>
      {
         Category => "TOR Events",
         Filter   => "CHAFilter0[8:0], (CHAFilter1[28:19] | CHAFilter1[18:9])",
         Desc     => "PCIe Data Traffic",
         Defn     => "Number of full PCI writes",
         Equation => "TOR_INSERTS.IO with:Cn_MSR_PMON_BOX_FILTER1.{opc0,not_nm,nm,all_opc,loc,rem}={0x248,1,1,0,1,1}",
      },
      "PCI_PARTIAL_WRITES" =>
      {
         Category => "TOR Events",
         Filter   => "(CHAFilter1[28:19] | CHAFilter1[18:9])",
         Desc     => "Partial PCI Writes",
         Defn     => "Number of partial PCI writes",
         Equation => "TOR_INSERTS.IO with:Cn_MSR_PMON_BOX_FILTER1.{opc0,not_nm,nm,all_opc,loc,rem}={0x200,1,1,0,1,1}",
      },
      "PCI_READS" =>
      {
         Category => "TOR Events",
         Filter   => "CHAFilter0[8:0], (CHAFilter1[28:19] | CHAFilter1[18:9])",
         Desc     => "Partial PCI Reads",
         Defn     => "Number of  PCI reads",
         Equation => "TOR_INSERTS.IO with:Cn_MSR_PMON_BOX_FILTER1.{opc0,not_nm,nm,all_opc,loc,rem}={0x21E,1,1,0,1,1}",
      },
      "PCT_RD_REQUESTS" =>
      {
         Category => "HA REQUEST Events",
         Filter   => "",
         Desc     => "Percent Read Requests",
         Defn     => "Percentage of HA traffic that is from Read Requests",
         Equation => "REQUESTS.READS / (REQUESTS.READS + REQUESTS.WRITES)",
      },
      "PCT_WR_REQUESTS" =>
      {
         Category => "HA REQUEST Events",
         Filter   => "",
         Desc     => "Percent Write Requests",
         Defn     => "Percentage of HA traffic that is from Write Requests",
         Equation => "REQUESTS.WRITES / (REQUESTS.READS + REQUESTS.WRITES)",
      },
      "STREAMED_FULL_STORES" =>
      {
         Category => "TOR Events",
         Filter   => "(CHAFilter1[28:19] | CHAFilter1[18:9])",
         Desc     => "Streaming Stores (Full Line)",
         Defn     => "Number of Streamed Store (of Full Cache Line) Transactions",
         Equation => "TOR_INSERTS.IA with:Cn_MSR_PMON_BOX_FILTER1.{opc0,not_nm,nm,all_opc,loc,rem}={0x20C,1,1,0,1,1}",
      },
      "STREAMED_PART_STORES" =>
      {
         Category => "TOR Events",
         Filter   => "(CHAFilter1[28:19] | CHAFilter1[18:9])",
         Desc     => "Streaming Stores (Partial Line)",
         Defn     => "Number of Streamed Store (of Partial Cache Line) Transactions",
         Equation => "TOR_INSERTS.IA with:Cn_MSR_PMON_BOX_FILTER1.{opc0,not_nm,nm,all_opc,loc,rem}={0x20D,1,1,0,1,1}",
      },
      "UC_READS" =>
      {
         Category => "TOR Events",
         Filter   => "(CHAFilter1[28:19] | CHAFilter1[18:9])",
         Desc     => "Uncacheable Reads",
         Defn     => "Uncachable Read Transactions",
         Equation => "TOR_INSERTS.IA_MISS with:Cn_MSR_PMON_BOX_FILTER1.{opc0,not_nm,nm,all_opc,loc,rem}={0x207,1,1,0,1,1}",
      },
   },
   "PCU Box Events" =>
   {
      "PCT_CYC_FREQ_CURRENT_LTD" =>
      {
         Category => "FREQ_MAX_LIMIT Events",
         Filter   => "",
         Desc     => "Percent Frequency Current Limited",
         Defn     => "Percentage of Cycles the Max Frequency is limited by current",
         Equation => "FREQ_MAX_CURRENT_CYCLES / CLOCKTICKS",
      },
      "PCT_CYC_FREQ_POWER_LTD" =>
      {
         Category => "FREQ_MAX_LIMIT Events",
         Filter   => "",
         Desc     => "Percent Frequency Power Limited",
         Defn     => "Percentage of Cycles the Max Frequency is limited by power",
         Equation => "FREQ_MAX_POWER_CYCLES / CLOCKTICKS",
      },
      "PCT_CYC_FREQ_THERMAL_LTD" =>
      {
         Category => "FREQ_MAX_LIMIT Events",
         Filter   => "",
         Desc     => "Percent Frequency Thermal Limited",
         Defn     => "Percentage of Cycles the Max Frequency is limited by thermal issues",
         Equation => "FREQ_MAX_CURRENT_CYCLES / CLOCKTICKS",
      },
      "s" =>
      {
         Category => "FREQ_MAX_LIMIT Events",
         Filter   => "",
         Desc     => "Percent Frequency OS Limited",
         Defn     => "Percentage of Cycles the Max Frequency is limited by the OS",
         Equation => "FREQ_MAX_OS_CYCLES / CLOCKTICKS",
      },
   },
   "UPI LL Box Events" =>
   {
      "DRS_E_FROM_UPI" =>
      {
         Category => "CTO Events",
         Filter   => "",
         Desc     => "DRS Data in F or E From UPI",
         Defn     => "DRS response in F or E states received from UPI in bytes.  To calculate the total data response for each cache line state, it's necessary to add the contribution from three flavors {DataC, DataC_FrcAckCnflt, DataC_Cmp} of data response packets for each cache line state.",
         Equation => "RxL_BASIC_HDR_MATCH.{umask,opc}={0x1C,1}  * 64",
      },
      "DRS_M_FROM_UPI" =>
      {
         Category => "CTO Events",
         Filter   => "",
         Desc     => "DRS Data_Ms From UPI",
         Defn     => "Data Response DataM packets received from UPI.  Expressed in bytes",
         Equation => "RxL_BASIC_HDR_MATCH.{umask,opc}={0x0C,1}  * 64",
      },
      "DRS_WB_FROM_UPI" =>
      {
         Category => "CTO Events",
         Filter   => "",
         Desc     => "DRS Writeback From UPI",
         Defn     => "DRS writeback packets received from UPI in bytes.  This is the sum of Wb{I,S,E} DRS packets",
         Equation => "DRS_WbI_FROM_UPI + DRS_WbS_FROM_UPI + DRS_WbE_FROM_UPI",
      },
      "DRS_WbE_FROM_UPI" =>
      {
         Category => "CTO Events",
         Filter   => "",
         Desc     => "DRS WbE From UPI",
         Defn     => "DRS writeback 'change M to E state' packets received from UPI in bytes",
         Equation => "RxL_BASIC_HDR_MATCH.{umask,opc}={0x2D,1}  *64",
      },
      "DRS_WbI_FROM_UPI" =>
      {
         Category => "CTO Events",
         Filter   => "",
         Desc     => "DRS WbI From UPI",
         Defn     => "DRS writeback 'change M to I state' packets received from UPI in bytes",
         Equation => "RxL_BASIC_HDR_MATCH.{umask,opc}={0x0D,1}  *64",
      },
      "DRS_WbS_FROM_UPI" =>
      {
         Category => "CTO Events",
         Filter   => "",
         Desc     => "DRS WbSFrom UPI",
         Defn     => "DRS writeback 'change M to S state' packets received from UPI in bytes",
         Equation => "RxL_BASIC_HDR_MATCH.{umask,opc}={0x1D,1}  *64",
      },
      "NCB_DATA_FROM_UPI_TO_NODEx" =>
      {
         Category => "CTO Events",
         Filter   => "",
         Desc     => "NCB Data From UPI To Node x",
         Defn     => "NCB Data packets (Any - Interrupts) received from UPI sent to Node ID 'x'.  Expressed in bytes",
         Equation => "RxL_BASIC_HDR_MATCH.{umask,endnid,dnid} = {0xE,1,x} * 64",
      },
      "PCT_LINK_CRC_RETRY_CYCLES" =>
      {
         Category => "CRC_ERRORS_RX Events",
         Filter   => "",
         Desc     => "Percent Link CRC Retry Cycles",
         Defn     => "Percent of Cycles the UPI link layer is in retry mode due to CRC errors",
         Equation => "RxL_CRC_CYCLES_IN_LLR / CLOCKTICKS",
      },
      "PCT_LINK_FULL_POWER_CYCLES" =>
      {
         Category => "POWER_RX Events",
         Filter   => "",
         Desc     => "Percent Link Full Power Cycles",
         Defn     => "Percent of Cycles the UPI link is at Full Power",
         Equation => "RxL0_POWER_CYCLES / CLOCKTICKS",
      },
      "PCT_LINK_HALF_DISABLED_CYCLES" =>
      {
         Category => "POWER_RX Events",
         Filter   => "",
         Desc     => "Percent Link Half Disabled Cycles",
         Defn     => "Percent of Cycles the UPI link in power mode where 60% of the lanes are disabled.",
         Equation => "RxL0P_POWER_CYCLES / CLOCKTICKS",
      },
      "PCT_LINK_SHUTDOWN_CYCLES" =>
      {
         Category => "POWER Events",
         Filter   => "",
         Desc     => "Percent Link Shutdown Cycles",
         Defn     => "Percent of Cycles the UPI link is Shutdown",
         Equation => "L1_POWER_CYCLES / CLOCKTICKS",
      },
      "UPI_SPEED" =>
      {
         Category => "CFCLK Events",
         Filter   => "",
         Desc     => "UPI Speed",
         Defn     => "UPI Speed - In GT/s (GigaTransfers / Second) - Max  UPI Bandwidth is 2 * ROUND ( UPI Speed , 0)",
         Equation => "ROUND (( CLOCKTICKS / TSC ) * TSC_SPEED, 0 ) * ( 8 / 1000)",
      },
   },
   "iMC Box Events" =>
   {
      "MEM_BW_READS" =>
      {
         Category => "PRE Events",
         Filter   => "",
         Desc     => "Read Memory Bandwidth",
         Defn     => "Memory bandwidth consumed by reads.  Expressed in bytes.",
         Equation => "(CAS_COUNT.RD * 64)",
      },
      "MEM_BW_TOTAL" =>
      {
         Category => "PRE Events",
         Filter   => "",
         Desc     => "Total Memory Bandwidth",
         Defn     => "Total memory bandwidth.  Expressed in bytes.",
         Equation => "MEM_BW_READS + MEM_BW_WRITES",
      },
      "MEM_BW_WRITES" =>
      {
         Category => "PRE Events",
         Filter   => "",
         Desc     => "Write Memory Bandwidth",
         Defn     => "Memory bandwidth consumed by writes  Expressed in bytes.",
         Equation => "(CAS_COUNT.WR * 64)",
      },
      "PCT_CYCLES_CRITICAL_THROTTLE" =>
      {
         Category => "POWER Events",
         Filter   => "",
         Desc     => "Percent Cycles Critical Throttle",
         Defn     => "The percentage of cycles all DRAM ranks in critical thermal throttling",
         Equation => "POWER_CRITICAL_THROTTLE_CYCLES / MC_Chy_PCI_PMON_CTR_FIXED",
      },
      "PCT_CYCLES_DLLOFF" =>
      {
         Category => "POWER Events",
         Filter   => "",
         Desc     => "Percent Cycles DLOFF",
         Defn     => "The percentage of cycles all DRAM ranks in CKE slow (DLOFF) mode",
         Equation => "POWER_CHANNEL_DLLOFF / MC_Chy_PCI_PMON_CTR_FIXED",
      },
      "PCT_CYCLES_DRAM_RANKx_IN_CKE" =>
      {
         Category => "POWER Events",
         Filter   => "",
         Desc     => "Percent Cycles DRAM Rank x in CKE",
         Defn     => "The percentage of cycles DRAM rank (x) spent in CKE ON mode.",
         Equation => "POWER_CKE_CYCLES.RANKx / MC_Chy_PCI_PMON_CTR_FIXED",
      },
      "PCT_CYCLES_DRAM_RANKx_IN_THR" =>
      {
         Category => "POWER Events",
         Filter   => "",
         Desc     => "Percent Cycles DRAM Rank x in CKE",
         Defn     => "The percentage of cycles DRAM rank (x) spent in thermal throttling.",
         Equation => "POWER_THROTTLE_CYCLES.RANKx / MC_Chy_PCI_PMON_CTR_FIXED",
      },
      "PCT_CYCLES_PPD" =>
      {
         Category => "POWER Events",
         Filter   => "",
         Desc     => "Percent Cycles PPD",
         Defn     => "The percentage of cycles all DRAM ranks in PPD mode",
         Equation => "POWER_CHANNEL_PPD / MC_Chy_PCI_PMON_CTR_FIXED",
      },
      "PCT_CYCLES_SELF_REFRESH" =>
      {
         Category => "POWER Events",
         Filter   => "",
         Desc     => "Percent Cycles Self Refresh",
         Defn     => "The percentage of cycles Memory is in self refresh power mode",
         Equation => "POWER_SELF_REFRESH / MC_Chy_PCI_PMON_CTR_FIXED",
      },
      "PCT_RD_REQUESTS" =>
      {
         Category => "RPQ Events",
         Filter   => "",
         Desc     => "Percent Read Requests",
         Defn     => "Percentage of read requests from total requests.",
         Equation => "RPQ_INSERTS / (RPQ_INSERTS + WPQ_INSERTS)",
      },
      "PCT_REQUESTS_PAGE_EMPTY" =>
      {
         Category => "ACT Events",
         Filter   => "",
         Desc     => "Percent Requests Page Empty",
         Defn     => "Percentage of memory requests that resulted in Page Empty",
         Equation => "(ACT_COUNT - PRE_COUNT.PAGE_MISS)/ (CAS_COUNT.RD + CAS_COUNT.WR)",
      },
      "PCT_REQUESTS_PAGE_HIT" =>
      {
         Category => "ACT Events",
         Filter   => "",
         Desc     => "Percent Requests Page Hit",
         Defn     => "Percentage of memory requests that resulted in Page Hits",
         Equation => "1 - (PCT_REQUESTS_PAGE_EMPTY + PCT_REQUESTS_PAGE_MISS)",
      },
      "PCT_REQUESTS_PAGE_MISS" =>
      {
         Category => "PRE Events",
         Filter   => "",
         Desc     => "Percent Requests Page Miss",
         Defn     => "Percentage of memory requests that resulted in Page Misses",
         Equation => "PRE_COUNT.PAGE_MISS / (CAS_COUNT.RD + CAS_COUNT.WR)",
      },
      "PCT_WR_REQUESTS" =>
      {
         Category => "WPQ Events",
         Filter   => "",
         Desc     => "Percent Write Requests",
         Defn     => "Percentage of write requests from total requests.",
         Equation => "WPQ_INSERTS / (RPQ_INSERTS + WPQ_INSERTS)",
      },
   },
   "rxl_hdr" =>
   {
      "AVG_DEMAND_RD_MISS_REMOTE_LATENCY" =>
      {
         Category => "TOR Events",
         Filter   => "(CHAFilter1[28:19] | CHAFilter1[18:9]), CHAFilter1[1:0]",
         Desc     => "Average Data Read Remote Miss Latency",
         Defn     => "Average Latency of Data Reads from an iA Core that miss the LLC and were satsified by a Remote cache or Remote Memory",
         Equation => "(TOR_OCCUPANCY.IA_MISS / TOR_INSERTS.IA_MISS) with:Cn_MSR_PMON_BOX_FILTER1.{opc0,not_nm,nm,all_opc,loc,rem}={0x202,1,1,0,0,1}",
      },
   },
);
